If you've been following semiconductor news recently, you've likely encountered a hot topic: CoWoS. In August 2026, TSMC announced at the OCP APAC Summit that its 5.5x reticle CoWoS packaging products have achieved stable yields between 98% and 99%. NVIDIA alone has secured over 50% of TSMC's total capacity for 2026.
But for PCB engineers and hardware developers, a more relevant question is: What does the rise of advanced packaging mean for PCB design? The answer may be more direct than you think.
CoWoS stands for Chip-on-Wafer-on-Substrate, TSMC's core 2.5D advanced packaging technology. Simply put, it uses a silicon interposer as a bridge to integrate logic chips, HBM memory, I/O, and other chiplets — each potentially fabricated on different process nodes — into a single package, enabling high-bandwidth, low-latency interconnection.
First applied to Xilinx FPGAs in 2012, CoWoS has now become the "standard" for AI chip vendors including NVIDIA, AMD, Google, and Amazon. A single AI chip often needs to connect to 6, 8, or even more HBM stacks. The coarse line widths of traditional PCBs cannot meet the transmission requirements; only the ultra-fine lines of the silicon interposer can handle the massive data throughput — measured in terabytes per second.
TSMC's achievement of 98-99% yield for 5.5x reticle CoWoS packaging is a significant technical breakthrough. According to its roadmap, TSMC aims to further expand packaging dimensions to a 14x reticle specification by 2029, enabling a single package to accommodate 10+ compute chiplets and 20+ HBM stacking modules.
To meet AI customer demand, TSMC's CoWoS capacity is entering a phase of ultra-rapid expansion. Industry estimates project monthly capacity will reach 140,000 wafers by the end of 2026, rising to 220,000 wafers in 2027. The compound annual growth rate (CAGR) for capacity from 2022 to 2027 exceeds 80%.
The continued expansion of CoWoS package sizes introduces new challenges for downstream PCB design. This is not just "a packaging issue" — it directly impacts the work of PCB engineers.
At the 14x reticle specification, package substrates can reach 100×100mm in size. Larger substrates mean larger BGA pad arrays and more pins on the PCB, increasing the complexity of placement and routing.
Impact on PCB design:
Larger BGAs require more signal and power layers to accommodate fanout
Decoupling capacitor placement space is further compressed
Stackup design requires more precise impedance control for high-speed signal transmission
High-end ABF substrates have already been upgraded to 18-20 layers. PCB manufacturers need higher processing precision and more mature process control capabilities.
Impact on PCB manufacturing:
Higher layer count boards demand tighter layer-to-layer registration accuracy
Large substrates are prone to deformation during multiple lamination cycles — expansion/shrinkage control becomes critical
Microvia alignment becomes more difficult, requiring more advanced laser drilling and inspection equipment
Shortages in ABF substrates and HBM supply make AI chip delivery timelines difficult to guarantee. This uncertainty is propagating upstream — PCB manufacturing is also feeling the supply chain pressure.
Given the rapid evolution of advanced packaging technologies, hardware engineers should prepare across several dimensions:
CoWoS-L, CoWoS-R, CoWoP, EMIB — each technology path has its own trade-offs in performance, cost, and size.
| Technology | Interposer/Medium | Key Characteristics |
|---|---|---|
| CoWoS-S | Silicon interposer | High cost, limited to 3.3x reticle (NVIDIA Hopper, AMD MI300) |
| CoWoS-R | Organic polymer RDL | Lower cost, 9x reticle by 2027 (Edge AI, Amazon Trainium) |
| CoWoS-L | LSI silicon bridge + RDL | Supports 12 HBM stacks, next-gen mainstream (NVIDIA Blackwell) |
| CoWoP | PCB-like substrate | Better SI, better cooling, lower cost (NVIDIA Rubin in testing) |
Understanding these differences helps in making more informed decisions during chip selection and system design.
AI chip package sizes are continuously increasing. PCB designs must reserve sufficient layout space and layer count margins, and PCB manufacturers must have the capability to handle higher layer counts and finer precision.
For engineers designing AI-related PCBs, we recommend early communication with your PCB manufacturer on:
Whether the stackup can support 20+ layers with tight impedance tolerances
The manufacturer's layer registration accuracy and expansion/shrinkage control capabilities
Experience with large-format substrates
ABF substrate and HBM supply shortages are unlikely to ease in the short term. Project planning should account for longer lead times on critical materials and consider alternative sourcing strategies.
CoWoS advanced packaging technology is driving continued breakthroughs in AI compute performance, while simultaneously reshaping downstream PCB design and manufacturing. Larger package sizes, higher layer counts, and tighter precision requirements demand new capabilities from hardware engineers and PCB manufacturers alike.
Understanding packaging technology trends and communicating design constraints with your PCB manufacturer early are essential steps for successful project execution.
Designing AI-related high-speed PCBs?
AnyPCBA has over a decade of experience in PCB manufacturing. We support 2-64 layers, including HDI, rigid-flex, and high-frequency hybrid technologies, to meet the demands of high-density, high-layer-count designs.
Our engineering team provides DFM design reviews before production, helping you identify potential issues in layout, stackup, and impedance control — essential as AI chip package sizes continue to grow.
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